Automatic status assignment logic circuit apparatus for bay devices

ABSTRACT

In accordance with the present invention, the circuit apparatus has a first and a second connection point each for respectively connecting to the first bay and second bay for communicating with them to determine which device in the bays is the master device. The circuit apparatus also has a third and a fourth connection point both of them for connecting to the first bay or second bay for receiving the Boolean algebra to determine which device is the master device. The circuit apparatus further has a fifth connection point for determining whether the circuit apparatus works.

FIELD OF THE INVENTION

[0001] The present invention relates in general to a logical circuitapparatus for computer systems. In particular, the present inventionprovides a logical circuit apparatus that is capable of automaticallyassigning the master/slave status of the devices in the first device bayand the second device bay of a computer.

BACKGROUND OF THE INVENTION

[0002] Computer users are placing a growing demand on their computers'storage capabilities. As operating systems and programs increase incomplexity, power and size, as users store greater amounts ofinformation, and as that information becomes more complex, space on thecomputer's hard disk drive is quickly used up. In order to gain morestorage capacity, many users desire to add a second storage apparatus,such as a hard disk drive, CD drives or DVD drives, to their system.

[0003] Device Bay, which is receiving broad industry acceptance, definesan industry specification for interchangeable peripheral devices, suchas hard disk drives, modems, network adapters, CD drives, DVD drives anda variety of other electronics devices. Any peripheral can be pluggedinto the Device Bay without users having to open the PC box or switch itoff. It will allow devices to be daisy-chained and software will takecare of which interface is used by the device. With Device Bay, a userwould be able to insert a peripheral like a DVD drive directly into a PCwithout opening, rebooting or turning off the PC.

[0004] One of the most popular ways to connect a second storageapparatus to a personal computer system is on the IDE bus. IDE(Integrated Drive Electronics) is a standard electronic interface usedbetween a computer motherboard's data paths or bus and the computer'sstorage devices. The IDE interface is based on the IBM PC IndustryStandard Architecture (ISA) 16-bit bus standard, but it is also used incomputers that use other bus standards. The IDE interface was originallydesigned as a hard disk drive interface that could handle only twophysical drives. One or two IDE drive units may be present on each IDEcontroller. When two drives are installed, they are cascaded on a commondata/control cable, with one assigned as the master, and the other asthe slave drive. Either of the two installed drives can be configured asthe master or the slave drive via the setting of one or more switches,or more commonly Berg jumpers, on the electronic printed circuit boardof the drives.

[0005] To use one drive as a master drive or a first drive and the otherdrive as a slave drive, or a second drive, control signals indicating amaster and a slave must be supplied to IDE controllers for these drives.When a controller detects the control signal indicating a master, thatdrive operates as a master drive. On the other hand, when a controllerdetects the control signal indicating a slave, then that drive operatesas a slave drive.

[0006] However, the configuration of the master and slave drives in theprimary and secondary cascades of a conventional IDE interface can beadjusted only by physically changing a drive jumper setting and thecabling. In other words, if the first device bay is fixed for the masterdrive and the second device bay for the slave drive, such assignmentrequires that the floppy disk or other devices not supporting the IDEinterface have to plug into the second device bay. Such requirementlimits the hardware configuration being easily upgrade because thespecific device needs to be plugged into the specific device bay. Thereis therefore a great need for a computer system that may automaticallyassign the master/slave status of devices in the first device bay andthe second device bay of a computer. The user is then freed fromworrying about where is the master device between the first and secondbays and the computer system is consequently easier to upgrade and use.

SUMMARY OF THE INVENTION

[0007] It is therefore an object of the present invention to provide aselective circuit to automatically assign the master/slave status ofdevices in the first device bay and the second device bay. It is capableof ensuring normally performance of this computer system even when afloppy disk is inserted into the first device bay.

[0008] It is therefore an object of the present invention to provide acircuit apparatus for selecting the master and slave configuration of anIDE interface.

[0009] It is another object of the present invention to provide anautomatically assigning circuit apparatus which is capable offacilitating the upgrade of computer system.

[0010] The present invention achieves the above-identified objects byproviding a logical circuit apparatus for selecting the master and slaveconfiguration of an IDE interface between the first and second bays. Inaccordance with the present invention, the logical circuit apparatus hasa first and a second connection point each for respectively connectingto the first bay and second bay connector for assigning them which isthe master device. The circuit apparatus also has a third and a fourthconnection points both of them for connecting to the first bay or secondbay connector for receiving the Boolean algebra to determine whichdevice in these bays is the master device. The circuit apparatus furtherhas a fifth connection point for determining whether the circuitapparatus works.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0012]FIG. 1 shows a block diagram of the device bay system according tothe first preferred embodiment the present invention;

[0013]FIG. 2 shows a detail drawing of the logical circuit apparatus ofthe present invention;

[0014]FIG. 3 shows a block diagram of the device bay system according tothe second preferred embodiment the present invention;

[0015]FIG. 4A shows the setting of the Boolean algebra value of the baydevices in the present invention; and

[0016]FIG. 4B shows the setting of the Boolean algebra value of the IDEstatus in the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] Without limiting the spirit and scope of the present invention,the circuit apparatus applied in computer system for automaticallyassigning the master/slave status of devices in the first device bay andthe second device bay of a computer in the present invention isillustrated with preferred embodiments.

[0018] The present invention satisfies this above need by adding aselective circuit apparatus. FIG. 1 shows a block diagram of the devicebay system according to the present invention. In FIG. 1, two baydevices 22 and 24 by connected by an IDE bus 20. The IDE bus 20 is thusa means of communication between the two bay devices 22 and 24. The twobay devices 22 and 24, first bay device and second bay device, arerespectively connected with the first-bay connector 32 and thesecond-bay connector 34. The IDE bus 20 is comprised of a standardcollection of signals for communicating data, commands and status. Oneof these signals includes the Pass Diagnostics signal (PDIAG*)transmitted by the interface line 26.

[0019] In accordance with the hot plugging technology of the device bay,the first bay or the second bay could be plugged with an IDE device or anon-IDE device. Therefore, if this original set of this computer systemis that the first bay device 24 is the master device and the second baydevice 22 is the slave device, this computer system will be in anabnormal situation when the first bay connector 32 is plugged by anon-IDE device and the second bay connector 30 is plugged by a IDEdevice. This present invention provides a logic circuit apparatus tosolve this above problem.

[0020] Please referring to FIG. 1 again, the apparatus for automaticassigning the master and the slave device of an IDE interface of acomputer system, in accordance with a preferred embodiment of thepresent invention, comprises a logical circuit apparatus 10 that isinserted between the first bay connector 32 and the second bay connector30. The logical circuit apparatus 10 comprising one function toautomatic assign the master and slave configuration between the firstbay device and the second bay device. The automatic assignment functionis responsible for a non-IDE device plugged into the bay whose originalset is for IDE device. Signal in relation to the swap of the master andslave device is handled.

[0021] As seen in FIG. 1, the number 1 to 5 represents the connectionpoints. The logical circuit apparatus 10 has a first connection point 1for connecting with the first bay connector 32 through the interfaceline 38 and a second connection point 2 for connecting with the secondbay connector 30 by the interface lines 36. The main function of the twointerface lines 36 and 38 is to assign the two bay devices which one isthe master device. In accordance with the preferred embodiment of thepresent invention, if a Boolean algebra value “0” is assigned to theconnection point 2 and a Boolean algebra value “1” is assigned to theconnection point 1, the IDE status of the device inserted into thesecond bay connector 30 will be a master and the device inserted intothe first bay connector 32 will be a slave. On the other hand, if aBoolean algebra value “1” is assigned to the connection point 2 and aBoolean algebra value “0” is assigned to the connection point 1, the IDEstatus of the device inserted into the second bay connector 30 will be aslave and the device inserted into the first bay connector 32 will be amaster.

[0022] The logical circuit apparatus 10 also has a third and a fourthconnection points 3 and 4 both of them through the interface lines 40and 42 to connect to the first bay connector 32 for receiving theBoolean algebra to determine which device in these device bays is themaster device. It is notice that the third and a fourth connectionpoints also may be connected to the second bay connector 30 if theoriginal setting of the computer system is that the second bay device isthe master device. On the other hand, the Boolean algebra value isdetermined by the device plugged into the first bay connector 32, whichis received by the logical circuit apparatus 10 via interface lines 40and 42. In accordance with the preferred embodiment, the Boolean algebravalue of the IDE bay device is set to (1,0) or (0,1) and the non-IDE baydevice is set to (0,0).

[0023] The logical circuit apparatus 10 further has a fifth connectionpoint for connecting with the first bay connector 32 through aninterface line 44 for determining whether the circuit apparatus works.In accordance with the present invention, a 3V voltage is applied to theinterface line 44 as shown in FIG. 1 to shut down the logical circuitapparatus 10. On the other hand, when a device, no matter an IDE or anon-IDE device, is inserted into the first bay connector 32, the applied3V voltage will be pulled down to zero to start up the logical circuitapparatus 10.

[0024] Please referring to FIG. 2, it shows a detail drawing of thelogical circuit apparatus 10 and the number 1 to 5 represents theconnection points. When a device is plugged into the first bayconnector, the set Boolean algebra value of the device will be sent tothe connection points 3 and 4 of the OR gate 202. In accordance with thepreferred embodiment of the present invention, the Boolean algebra valueis (0,0) if the inserted device is a non-IDE device. On the other hand,the Boolean algebra value is (0,1) or (1,0) if the inserted device is anIDE device.

[0025] If a non-IDE device, a floppy drive, is inserted into the firstbay connector, the Boolean algebra value (0,0) will be respectively sentto the connection points 3 and 4, and the OR gate 202 will output a lowvoltage to the emitter electrode of the bipolar junction transistor 204(BJT). On the other hand, the connection point 5 will be pull downbecause a device is inserted into the first bay connector. At the sametime, the pull down voltage will conduct the transistor 204. Theoutputted low voltage of the OR gate 202 will pass through thetransistor 204 to apply to the base electrode of the transistor 206. Thelow voltage will not conduct the transistor 206. Therefore, the highvoltage 5V will be direct applied to the base electrode of thetransistor 208 to conduct the transistor 208. Because the transistor 208is conducted, the voltage value of the connection point 2 will be pulldown to zero. On the other hand, the voltage value of the connectionpoint 1 depends on the resistance value of the resistance R₁ and R₂.However, the connection point 1 may be designed to represent a highvoltage. Therefore, the connection point 1 will represent acorresponding “high” voltage, the Boolean algebra value “1”, and theconnection point 2 will represent a corresponding “low” voltage, theBoolean algebra value “0”. In accordance with the configuration designof the present invention, the connection point 1 and the connectionpoint 2 will always represent the different Boolean algebra value. Forexample, if the connection point 1 represents the Boolean algebra value“1”, the connection point 2 will represent the Boolean algebra value“0”, in vice versa. Therefore, the IDE status of the device insertedinto the second bay connector 30 will be a master and the deviceinserted into the first bay connector 32 will be a slave.

[0026] Although this original set of this computer system is that thefirst bay device 24, please referring to FIG. 1, is the master device,the logical circuit apparatus 10 of the present invention will switchthe second bay device as the master device if the device plugged intothe first bay connector 32 is a non-IDE device.

[0027] On the other hand, please still referring to FIG. 2, if an IDEdevice, an IDE hard disc or an IDE CD ROM, is inserted into the firstbay connector, the Boolean algebra value (1,0) or (0,1) will berespectively sent to the connection points 3 and 4. Then, the OR gate202 will output a high voltage to the emitter electrode of the bipolarjunction transistor 204 (BJT). On the other hand, the connection point 5will be pull down and conduct the transistor 204. The high voltageoutputted from the OR gate 202 will pass through the transistor 204 toconduct the transistor 206. Then, the connection point 1 will be pulldown to zero, the Boolean algebra value “0”. The zero voltage will notconduct the transistor 208, therefore, the connection point 2 willrepresent high voltage, the Boolean algebra value “1”. In other words,the IDE status of the device inserted into the second bay connector 30will be a slave and the device inserted into the first bay connector 32will be a master which is same as the original set of this computersystem.

[0028] Please refer to FIG. 3, it shows another preferred embodiment ofthe present invention. The number 1 to 5 represents the connectionpoints. The first connection point 1 is connected with the second bayconnector 30 through the interface line 36 and the second connectionpoint 2 is connected with the first bay connector 32 by the interfacelines 38. In accordance with the another preferred embodiment of thepresent invention, if a Boolean algebra value “1” is assigned to theconnection point 2 and a Boolean algebra value “0” is assigned to theconnection point 1, the IDE status of the device inserted into thesecond bay connector 30 will be a master and the device inserted intothe first bay connector 32 will be a slave. On the other hand, if aBoolean algebra value “0” is assigned to the connection point 2 and aBoolean algebra value “1” is assigned to the connection point 1, the IDEstatus of the device inserted into the second bay connector 30 will be aslave and the device inserted into the first bay connector 32 will be amaster.

[0029] Please refer to FIG. 3 again, the third and a fourth connectionpoints 3 and 4 both of them through the interface lines 50 and 52 toconnect to the second bay connector 30 for receiving the Boolean algebrato determine which device in these device bays is the master device. Thereceived Boolean algebra value is received via interface lines (50 and52) and determined by the device plugged into the second bay connector30. In accordance with the another preferred embodiment, the Booleanalgebra value of the IDE bay device is set to (1,0) or (0,1) and thenon-IDE bay device is set to (0,0).

[0030] In accordance with the preferred embodiment of the presentinvention, this original set of this computer system is that the secondbay device 22 is the master device and the first bay device 24 is theslave device. Therefore, the logical circuit apparatus 10 of the presentinvention will switch the first bay device 24 as the master device ifthe device plugged into the second bay connector 30 is a non-IDE device.

[0031] For example, please referring to FIG. 2 again, if a non-IDEdevice, such as a floppy drive, is inserted into the second bayconnector 30, the Boolean algebra value (0,0) will be respectively sentto the connection points 3 and 4. Then, the OR gate 202 will output alow voltage to the emitter electrode of the bipolar junction transistor204 (BJT). The connection point 5 will be pull down and conduct thetransistor 204. The low voltage outputted from the OR gate 202 will passthrough the transistor 204 to apply to the transistor 206. This voltagewill not conduct the transistor 206. Therefore, the connection point 1will be pull up to high, the Boolean algebra value “1”. The high voltagewill conduct the transistor 208, therefore, the connection point 2 willbe pull down to zero, the Boolean algebra value “0”. In other words, theIDE status of the device inserted into the second bay connector 30 willbe a slave and the device inserted into the first bay connector 32 willbe a master. The logic circuit apparatus of the present invention mayautomatic assign the master and slave status of the bay device.Therefore, the configuration selection signals in the connection points1 and 2 may be generated by the logical circuit apparatus 10.

[0032] In accordance with the circuit design as shown in the FIG. 2 ofthe present invention, the connection point 1 and the connection point 2will always represent the different Boolean algebra value. For example,if the connection point 1 represents the Boolean algebra value “1”, theconnection point 2 will represent the Boolean algebra value “0”, in viceversa.

[0033] In accordance with the two embodiments of the present invention,please referring to FIG. 4A, it shows the setting of the Boolean algebravalue in the present invention. In accordance with the presentinvention, the Boolean algebra value of the non-IDE device, floppydrive, is (0,0). The Boolean algebra value of the IDE device, hard disc,is (0,1) and the Boolean algebra value of the IDE device, CD or DVD ROM,is (1,0). On the other hand, the FIG. 4B shows the setting of the IDEstatus. In accordance with the two embodiments, the Boolean algebravalue “0” represents the IDE status is master. The Boolean algebra value“1” represents the IDE status is slave.

[0034] As is understood by a person skilled in the art, the foregoingtwo preferred embodiments of the present invention are illustrative ofthe present invention rather than limiting of the present invention.They are intended to cover various modifications and similararrangements included within the spirit and scope of the appendedclaims, for example, the logic circuit apparatus is not just only thiskind of design as described in the above, the other circuit designhaving the same function also may be used in this present invention. Thescope of which should be accorded the broadest interpretation so as toencompass all such modifications and similar structure.

What is claimed is:
 1. An automatic assignment logical circuit apparatusfor selecting a master device and a slave device from among a first baydevice and a second bay device, wherein said first bay device beingconnected to the first bay connector and said second bay device beingconnected to the second bay connector, and said first bay connector andsaid second bay connector are in cascaded, said automatic assignmentlogical circuit apparatus comprising: first and second connection pointsfor electrically connecting to said first bay connector and said secondbay connector respectively, wherein said first and second connectionpoints for assigning said first bay connector and said second bayconnector as one of the master device connector and the slave deviceconnector respectively and the slave device connector and the masterdevice connector respectively; third and fourth connection points forelectrically connecting to said first bay connector, wherein said thirdand fourth connection points for receiving a pair of Boolean algebravalue from said first bay connector and sent two Boolean algebra valuesto said first and second connection points respectively to assign one ofsaid first and second bay connectors as the master device connector andthe other as the slave device connector, wherein said two Booleanalgebra values are different; and fifth connection point forelectrically connecting to said first bay connector and a referencevoltage applied to said fifth connection point, wherein said fifthconnection point for starting said logical circuit apparatus when afirst bay device is plugged into said first bay connector and stoppingsaid logical circuit apparatus when said first bay device is pulled outsaid first bay connector.
 2. The automatic assignment logical circuitapparatus according to claim 1, wherein said pair of Boolean algebravalue is related to the device plugged into said first bay connector. 3.The automatic assignment logical circuit apparatus according to claim 1,wherein said pair of Boolean algebra value is (0,0) when the deviceplugged into said first bay connector is a non-IDE device.
 4. Theautomatic assignment logical circuit apparatus according to claim 1,wherein said pair of Boolean algebra value is (1,0) or (0,1) when thedevice plugged into said first bay connector is an IDE device.
 5. Theautomatic assignment logical circuit apparatus according to claim 1,wherein said first bay connector is the master device connector when theBoolean algebra value received by the first connection point is “0”. 6.The automatic assignment logical circuit apparatus according to claim 1,wherein said first bay connector is the slave device connector when theBoolean algebra value received by the first connection point is “1”. 7.The automatic assignment logical circuit apparatus according to claim 1,wherein said second bay connector is the master device connector whenthe Boolean algebra value received by the second connection point is“0”.
 8. The automatic assignment logical circuit apparatus according toclaim 1, wherein said second bay connector is the slave device connectorwhen the Boolean algebra value received by the second connection pointis “1”.
 9. An automatic assignment logical circuit apparatus forselecting a master device and a slave device from among a first baydevice and a second bay device, wherein said first bay device beingconnected to the first bay connector and said second bay device beingconnected to the second bay connector, and said first bay connector andsaid second bay connector are in cascaded, said automatic assignmentlogical circuit apparatus comprising: An OR gate having first and secondconnection points for electrically connecting to said first bayconnector, wherein said first and second connection points for receivinga pair of Boolean algebra value from said first bay connector and outputa first Boolean algebra value; A first transistor having a emitterelectrode for receiving said first Boolean algebra value and having baseelectrode for electrically connecting to said first bay connector and areference voltage also applied to said base electrode, wherein saidfirst transistor will be conducted when a device is plugged into saidfirst bay connector to trigger said base electrode and said baseelectrode will not be triggered when a device is pulled out said firstbay connector; A second transistor having a base electrode for receivingsaid first Boolean algebra value passed through said first transistorand a collector electrode for electrically connecting to said first bayconnector, wherein said second transistor will be conducted when saidfirst Boolean algebra value having high level and generates a secondBoolean algebra value at said collector electrode for sending to saidfirst bay connector and a high voltage also applied to said collectorelectrode; and A third transistor having a base electrode for receivingsaid second Boolean algebra value passing through said second transistorand generating a third Boolean algebra value at said third transistor'scollector electrode which is electrically connected to said second bayconnector, wherein said third transistor will be conducted when saidsecond Boolean algebra value having high level and said generated thirdBoolean algebra value for sending to said second bay connector and ahigh voltage also applied to said collector electrode.
 10. The automaticassignment logical circuit apparatus according to claim 9, wherein saidpair of Boolean algebra value is related to the device plugged into saidfirst bay connector.
 11. The automatic assignment logical circuitapparatus according to claim 9, wherein said pair of Boolean algebravalue is (0,0) when the device plugged into said first bay connector isa non-IDE device.
 12. The automatic assignment logical circuit apparatusaccording to claim 9, wherein said pair of Boolean algebra value is(1,0) or (0,1) when the device plugged into said first bay connector isan IDE device.
 13. The automatic assignment logical circuit apparatusaccording to claim 9, wherein said first bay connector is the masterdevice connector when said second Boolean algebra value is “0”.
 14. Theautomatic assignment logical circuit apparatus according to claim 9,wherein said first bay connector is the slave device connector when saidsecond Boolean algebra value is “1”.
 15. The automatic assignmentlogical circuit apparatus according to claim 9, wherein said second bayconnector is the master device connector when said third Boolean algebravalue is “0”.
 16. The automatic assignment logical circuit apparatusaccording to claim 9, wherein said second bay connector is the slavedevice connector when said third Boolean algebra value is “1”.
 17. Theautomatic assignment logical circuit apparatus according to claim 9,wherein said second and third Boolean algebra value is different. 18.The automatic assignment logical circuit apparatus according to claim 9,wherein said first and second Boolean algebra value is different.